RISC-V (pronounced risk-five) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed at the University of California, Berkeley.

RISC-V members include processor IP developers implementing the RISC-V ISA, semiconductor vendors starting to use RISC-V cores on their SoCs, EDA companies helping with processor and SoC implementation and verification, software tool chain and OS companies working on various aspects of the RISC-V software ecosystem and software development tools companies, such as Imperas, helping with the porting, debug and testing of software running on RISC-V based devices. For more information about RISC-V, please visit https://riscv.org