Content for OVP Fast Processor Model Variant: ARM / MultiCluster

Multi Processor Debug of a platform including an Andes RISC-V N25 running FreeRTOS and ARM Cortex-A15MPx4 running SMP Linux
ARM Extendable Platform Kits and Tools Demo Video
Using the ARM DS-5 Debugger with Imperas simulators and models demonstration video
Continuous Integration and Test Automation with Jenkins
Sketch Cartoon Introduction to Imperas
ARM TrustZone Video Application Note
Simulating Andes RISC-V N25 running FreeRTOS and ARM Cortex-A15MPx4 running SMP Linux
ARM Bare Metal Demos Video Presentation
ARM Video Presentation of Booting uClinux/Linux
Video Presentation of SystemC TLM2.0 ARM Integrator Platform booting Linux
64 Bit and Multiple Quad Core Processors Video Demonstration
QuantumLeap Parallel Simulation using multi-core host PC gaining significant simulation speed.
Hetero 1xARM7 3xMIPS32LE Demonstration Video
Application Development and Debug using GDB / Eclipse Demonstration Video
RISC-V Custom Instruction Design and Verification Flow
Altera Nios II Bare Metal & Cyclone III Linux Booting Demo Video
Using the Green Hills Software MULTI Debugger with Imperas simulators and models demonstration video
on this link.

">DVCon 2021. A personal perspective on the history of SystemVerilog and Superlog

Imperas CEO Simon Davidmann Introducing Imperas Software
Information on Imperas at ARM TechCon 2016
DVCon 2021. 25 years after Verisity, verification is still evolving
Customer case study for AUDI Nira with the Imperas Solution of Software Testing in Automotive
(more videos)
IntegratorCP booting Linux on Cortex-A9UP
SystemC TLM2.0 IntegratorCP with Cortex-A9UP
Self contained ARM Cortex-A examples
TLM2.0 executable demos for ARM Cortex-A
Platform including ARM Cortex-A9MPx4 to run ARM MPCore Sample Code
Versatile Express booting Linux on Cortex-A9MP Single, Dual and Quad Core
Self contained ARM examples for ARM Classic, Cortex-A, Cortex-M and Cortex-R profile processors
Versatile Express booting Linux on Cortex-A15MP Single, Dual and Quad Core
Versatile Express booting Linux kernels on four Cortex-A15MP Quad Core processors
Self contained ARM examples utilizing the ARM v8 architecture
Self contained ARM examples utilizing the ARM AArch64 ARMv8 architecture
TLM2.0 executable demos
Main OVP Download including OVPsim Simulator and Self Contained Examples of all CPU Models using The
Versatile Express booting Linux on Cortex-A9MP Single, Dual and Quad Core
Versatile Express booting Linux on Cortex-A15MP Single, Dual and Quad Core
IntegratorCP booting Linux on ARM926EJ-S or Cortex-A9UP
Platform including ARM Cortex-A9MPx4 to run ARM MPCore Sample Code
Versatile Express booting Linux kernels on four Cortex-A15MP Quad Core processors
TLM2.0 executable demos
Self contained ARM Cortex-R examples
Self contained ARM Cortex-M3 examples
TLM2.0 executable demos for ARM Cortex-M3
Self contained ARM Cortex-M examples
TLM2.0 executable demos for ARM Cortex-M
ARM Cortex-M3 running Micrium uC/OS-II
ARM Cortex-M3 running FreeRTOS
ARM Cortex-M3 running Micrium uC/OS-II
ARM Cortex-M3 running FreeRTOS
Platform using FMv1 memory map booting Linux kernels on Cortex-A57MP processor
Platform using FMv1 memory map booting Linux kernels on Cortex-A53MP and Cortex-A57MP processor
Self contained ARM examples
IntegratorCP booting Linux
SystemC TLM2.0 IntegratorCP
IntegratorCP booting Nucleus
IntegratorCP with examples using the eCos operating system
TLM2.0 Platform using FMv1 memory map booting Linux kernels on Cortex-A53MP processor
IntegratorCP booting Nucleus
IntegratorCP with examples using the eCos operating system
Platform using FMv1 memory map booting Linux kernels on Cortex-A57MP and Cortex-A53MP processor big.
ARM7 and MIPS32 hetero multicore


OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions).
This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap

Traditionally, processor models and simulators make use of one thread on the host PC.
Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance.
To find out about the Imperas parallel simulation lookup Imperas QuantumLeap.
There are videos of QuantumLeap on ARM here,
and MIPS here.
For press information related to QuantumLeap for ARM click here
or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools

This model executes instructions of the target architecture and provides an interface for debug access.
An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface.
For more information watch the OVP video here.

The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for ARM MultiCluster

An ISS is a software development tool that takes in instructions for a target processor and executes them.
The heart of an ISS is the model of the processor.
Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model.
The Imperas ARM MultiCluster ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution.
The ARM MultiCluster ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and
Imperas debuggers.

Overview of ARM MultiCluster Fast Processor Model

Model Variant name: MultiCluster
    This model implements an ARM system containing clusters of MPCore processors communicating using a common GICv2 or GICv3 block.
    By default, the system contains Cortex-A53MPx4 and Cortex-A57MPx4 clusters, but this can be changed using parameter "override_clusterVariants". This parameter is a comma-separated list of cluster components (e.g. "Cortex-A53MPx4,Cortex-A57MPx4"). Note that if a GICv2 is selected, the total number of PEs must not exceed 8.
    This document describes the interface to the MultiCluster only. Refer to documentation of individual clusters for information regarding implemented features, licensing and limitations.
    By default, the model implements a GICv2. Parameter enableGICv3 can be used to select a GICv3 instead.

Model downloadable (needs registration and to be logged in) in package arm.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant MultiCluster is available OVP_Model_Specific_Information_arm_MultiCluster.pdf.


Location: The Fast Processor Model source and object file is found in the installation VLNV tree:
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0xb7
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)

Port Type Name Width (bits) Description
master DATA 32
master GICRegisters 32

SystemC Signal Ports (Net Ports)

Port Type Name Description
SPI32 input
SPI33 input
SPI34 input
SPI35 input
SPI36 input
SPI37 input
SPI38 input
SPI39 input
SPI40 input
SPI41 input
SPI42 input
SPI43 input
SPI44 input
SPI45 input
SPI46 input
SPI47 input
SPI48 input
SPI49 input
SPI50 input
SPI51 input
SPI52 input
SPI53 input
SPI54 input
SPI55 input
SPI56 input
SPI57 input
SPI58 input
SPI59 input
SPI60 input
SPI61 input
SPI62 input
SPI63 input
SPI64 input
SPI65 input
SPI66 input
SPI67 input
SPI68 input
SPI69 input
SPI70 input
SPI71 input
SPI72 input
SPI73 input
SPI74 input
SPI75 input
SPI76 input
SPI77 input
SPI78 input
SPI79 input
SPI80 input
SPI81 input
SPI82 input
SPI83 input
SPI84 input
SPI85 input
SPI86 input
SPI87 input
SPI88 input
SPI89 input
SPI90 input
SPI91 input
SPI92 input
SPI93 input
SPI94 input
SPI95 input
SPIVector input
periphReset input
EVENTI input
EVENTO output
PPI16_C0_0 input
PPI17_C0_0 input
PPI18_C0_0 input
PPI19_C0_0 input
PPI20_C0_0 input
PPI21_C0_0 input
PPI22_C0_0 input
PPI23_C0_0 input
PPI24_C0_0 input
PPI25_C0_0 input
PPI26_C0_0 input
PPI27_C0_0 input
PPI28_C0_0 input
PPI29_C0_0 input
PPI30_C0_0 input
PPI31_C0_0 input
CNTVIRQ_C0_0 output
CNTPSIRQ_C0_0 output
CNTPNSIRQ_C0_0 output
CNTPHPIRQ_C0_0 output
IRQOUT_C0_0 output
FIQOUT_C0_0 output
RVBARADDRx_C0_0 input
AA64nAA32_C0_0 input
VINITHI_C0_0 input
CFGEND_C0_0 input
CFGTE_C0_0 input
reset_C0_0 input
fiq_C0_0 input
irq_C0_0 input
sei_C0_0 input
vfiq_C0_0 input
virq_C0_0 input
vsei_C0_0 input
AXI_SLVERR_C0_0 input
CP15SDISABLE_C0_0 input
PMUIRQ_C0_0 output
SMPEN_C0_0 output
PPI16_C0_1 input
PPI17_C0_1 input
PPI18_C0_1 input
PPI19_C0_1 input
PPI20_C0_1 input
PPI21_C0_1 input
PPI22_C0_1 input
PPI23_C0_1 input
PPI24_C0_1 input
PPI25_C0_1 input
PPI26_C0_1 input
PPI27_C0_1 input
PPI28_C0_1 input
PPI29_C0_1 input
PPI30_C0_1 input
PPI31_C0_1 input
CNTVIRQ_C0_1 output
CNTPSIRQ_C0_1 output
CNTPNSIRQ_C0_1 output
CNTPHPIRQ_C0_1 output
IRQOUT_C0_1 output
FIQOUT_C0_1 output
RVBARADDRx_C0_1 input
AA64nAA32_C0_1 input
VINITHI_C0_1 input
CFGEND_C0_1 input
CFGTE_C0_1 input
reset_C0_1 input
fiq_C0_1 input
irq_C0_1 input
sei_C0_1 input
vfiq_C0_1 input
virq_C0_1 input
vsei_C0_1 input
AXI_SLVERR_C0_1 input
CP15SDISABLE_C0_1 input
PMUIRQ_C0_1 output
SMPEN_C0_1 output
PPI16_C0_2 input
PPI17_C0_2 input
PPI18_C0_2 input
PPI19_C0_2 input
PPI20_C0_2 input
PPI21_C0_2 input
PPI22_C0_2 input
PPI23_C0_2 input
PPI24_C0_2 input
PPI25_C0_2 input
PPI26_C0_2 input
PPI27_C0_2 input
PPI28_C0_2 input
PPI29_C0_2 input
PPI30_C0_2 input
PPI31_C0_2 input
CNTVIRQ_C0_2 output
CNTPSIRQ_C0_2 output
CNTPNSIRQ_C0_2 output
CNTPHPIRQ_C0_2 output
IRQOUT_C0_2 output
FIQOUT_C0_2 output
RVBARADDRx_C0_2 input
AA64nAA32_C0_2 input
VINITHI_C0_2 input
CFGEND_C0_2 input
CFGTE_C0_2 input
reset_C0_2 input
fiq_C0_2 input
irq_C0_2 input
sei_C0_2 input
vfiq_C0_2 input
virq_C0_2 input
vsei_C0_2 input
AXI_SLVERR_C0_2 input
CP15SDISABLE_C0_2 input
PMUIRQ_C0_2 output
SMPEN_C0_2 output
PPI16_C0_3 input
PPI17_C0_3 input
PPI18_C0_3 input
PPI19_C0_3 input
PPI20_C0_3 input
PPI21_C0_3 input
PPI22_C0_3 input
PPI23_C0_3 input
PPI24_C0_3 input
PPI25_C0_3 input
PPI26_C0_3 input
PPI27_C0_3 input
PPI28_C0_3 input
PPI29_C0_3 input
PPI30_C0_3 input
PPI31_C0_3 input
CNTVIRQ_C0_3 output
CNTPSIRQ_C0_3 output
CNTPNSIRQ_C0_3 output
CNTPHPIRQ_C0_3 output
IRQOUT_C0_3 output
FIQOUT_C0_3 output
RVBARADDRx_C0_3 input
AA64nAA32_C0_3 input
VINITHI_C0_3 input
CFGEND_C0_3 input
CFGTE_C0_3 input
reset_C0_3 input
fiq_C0_3 input
irq_C0_3 input
sei_C0_3 input
vfiq_C0_3 input
virq_C0_3 input
vsei_C0_3 input
AXI_SLVERR_C0_3 input
CP15SDISABLE_C0_3 input
PMUIRQ_C0_3 output
SMPEN_C0_3 output
PPI16_C1_0 input
PPI17_C1_0 input
PPI18_C1_0 input
PPI19_C1_0 input
PPI20_C1_0 input
PPI21_C1_0 input
PPI22_C1_0 input
PPI23_C1_0 input
PPI24_C1_0 input
PPI25_C1_0 input
PPI26_C1_0 input
PPI27_C1_0 input
PPI28_C1_0 input
PPI29_C1_0 input
PPI30_C1_0 input
PPI31_C1_0 input
CNTVIRQ_C1_0 output
CNTPSIRQ_C1_0 output
CNTPNSIRQ_C1_0 output
CNTPHPIRQ_C1_0 output
IRQOUT_C1_0 output
FIQOUT_C1_0 output
RVBARADDRx_C1_0 input
AA64nAA32_C1_0 input
VINITHI_C1_0 input
CFGEND_C1_0 input
CFGTE_C1_0 input
reset_C1_0 input
fiq_C1_0 input
irq_C1_0 input
sei_C1_0 input
vfiq_C1_0 input
virq_C1_0 input
vsei_C1_0 input
AXI_SLVERR_C1_0 input
CP15SDISABLE_C1_0 input
PMUIRQ_C1_0 output
SMPEN_C1_0 output
PPI16_C1_1 input
PPI17_C1_1 input
PPI18_C1_1 input
PPI19_C1_1 input
PPI20_C1_1 input
PPI21_C1_1 input
PPI22_C1_1 input
PPI23_C1_1 input
PPI24_C1_1 input
PPI25_C1_1 input
PPI26_C1_1 input
PPI27_C1_1 input
PPI28_C1_1 input
PPI29_C1_1 input
PPI30_C1_1 input
PPI31_C1_1 input
CNTVIRQ_C1_1 output
CNTPSIRQ_C1_1 output
CNTPNSIRQ_C1_1 output
CNTPHPIRQ_C1_1 output
IRQOUT_C1_1 output
FIQOUT_C1_1 output
RVBARADDRx_C1_1 input
AA64nAA32_C1_1 input
VINITHI_C1_1 input
CFGEND_C1_1 input
CFGTE_C1_1 input
reset_C1_1 input
fiq_C1_1 input
irq_C1_1 input
sei_C1_1 input
vfiq_C1_1 input
virq_C1_1 input
vsei_C1_1 input
AXI_SLVERR_C1_1 input
CP15SDISABLE_C1_1 input
PMUIRQ_C1_1 output
SMPEN_C1_1 output
PPI16_C1_2 input
PPI17_C1_2 input
PPI18_C1_2 input
PPI19_C1_2 input
PPI20_C1_2 input
PPI21_C1_2 input
PPI22_C1_2 input
PPI23_C1_2 input
PPI24_C1_2 input
PPI25_C1_2 input
PPI26_C1_2 input
PPI27_C1_2 input
PPI28_C1_2 input
PPI29_C1_2 input
PPI30_C1_2 input
PPI31_C1_2 input
CNTVIRQ_C1_2 output
CNTPSIRQ_C1_2 output
CNTPNSIRQ_C1_2 output
CNTPHPIRQ_C1_2 output
IRQOUT_C1_2 output
FIQOUT_C1_2 output
RVBARADDRx_C1_2 input
AA64nAA32_C1_2 input
VINITHI_C1_2 input
CFGEND_C1_2 input
CFGTE_C1_2 input
reset_C1_2 input
fiq_C1_2 input
irq_C1_2 input
sei_C1_2 input
vfiq_C1_2 input
virq_C1_2 input
vsei_C1_2 input
AXI_SLVERR_C1_2 input
CP15SDISABLE_C1_2 input
PMUIRQ_C1_2 output
SMPEN_C1_2 output
PPI16_C1_3 input
PPI17_C1_3 input
PPI18_C1_3 input
PPI19_C1_3 input
PPI20_C1_3 input
PPI21_C1_3 input
PPI22_C1_3 input
PPI23_C1_3 input
PPI24_C1_3 input
PPI25_C1_3 input
PPI26_C1_3 input
PPI27_C1_3 input
PPI28_C1_3 input
PPI29_C1_3 input
PPI30_C1_3 input
PPI31_C1_3 input
CNTVIRQ_C1_3 output
CNTPSIRQ_C1_3 output
CNTPNSIRQ_C1_3 output
CNTPHPIRQ_C1_3 output
IRQOUT_C1_3 output
FIQOUT_C1_3 output
RVBARADDRx_C1_3 input
AA64nAA32_C1_3 input
VINITHI_C1_3 input
CFGEND_C1_3 input
CFGTE_C1_3 input
reset_C1_3 input
fiq_C1_3 input
irq_C1_3 input
sei_C1_3 input
vfiq_C1_3 input
virq_C1_3 input
vsei_C1_3 input
AXI_SLVERR_C1_3 input
CP15SDISABLE_C1_3 input
PMUIRQ_C1_3 output
SMPEN_C1_3 output

No FIFO Ports in MultiCluster.


Name Code Description
Reset 0
Undefined 1
SupervisorCall 2
SecureMonitorCall 3
HypervisorCall 4
PrefetchAbort 5
DataAbort 6
HypervisorTrap 7
IllegalState 10
MisalignedPC 11
MisalignedSP 12
SError 13

Execution Modes

Mode Code Description
EL0t 0
EL1t 4
EL1h 5
EL2t 8
EL2h 9
EL3t 12
EL3h 13
User 16
FIQ 17
IRQ 18
Supervisor 19
Monitor 22
Abort 23
Hypervisor 26
Undefined 27
System 31

More Detailed Information

The MultiCluster OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_arm_MultiCluster.pdf.

Other Sites/Pages with similar information

Information on the MultiCluster OVP Fast Processor Model can also be found on other web sites:: has more information on the model library.