The MIPS32 74K core family is the industry's first fully synthesizable processor IP to surpass 1.5 GHz in TSMC 40nmG process using industry standard libraries and EDA flows. The 74K core family is based on a superscalar microarchitecture with out-of-order (OoO) instruction dispatch. The implementation features a 15-stage pipeline to achieve high synthesizable frequencies, and supports up to 4 instructions fetched per cycle, plus up to 4 instructions issued per cycle in the 74Kf core, the version in the family with a dual issue high performance floating point unit (FPU).

Processor Model Variants of MIPS / Classic / 74K