Imperas paper voted in top 5 at Cadence CDNlive users meeting

Cooley's CDNlive'12 Trip Report lists best papers. Fast Processor Models comes 4th

At the recent Cadence CDNlive event there were 95 papers presented and the conference attendees vote as to which papers they rate the best.

Imperas' Larry Lapides presented a paper on Fast Processor Models for SystemC Virtual Platforms and we were surprised and pleased that it was rated 4th best paper - the event is traditionally focused on silicon design, and yes the top 3 papers were related to that. So it just goes to show that the adoption of virtual platforms is becoming more and more important.

The paper introduced why multicore/multiprocessor software development fails using old techniques, and explains that initial usage of virtual platforms with multiple debuggers and multiple windows just made everything more painful. "No wonder that more than half of current embedded design projects are behind schedule ...".

The paper discussed SystemC Virtual Platforms and introduced the Imperas OVP Fast Processor Models, how they are constructed, used, and what is available.

The paper continued by discussing the library of models ranging from all the ARM Classic thru Cortex, the MIPS full range, Renesas, Xilinx, etc, and then explored use models based on the Cadence Virtual System Platform model of the Xilinx Zynq-7000 EPP using the Imperas OVP Fast Processor Model of the ARM Cortex-A9MPx2 core. The paper concluded by introducing some of the Imperas advanced software tools.

If you would like more information on the Imperas paper, please contact us at

More information on CDNlive can be found here.

More information on John Cooley's trip report can be found here. Scan down for 'Best Papers'.