Imperas Forms the OVP (Open Virtual Platform) Initiative

VDC Embedded Systems Practice, March 7th 2008
Posted by VDC Embedded Systems Practice
Friday, March 07, 2008 What Happened?

This week Imperas announced the release of its Open Virtual Platforms to �establish a common, open standard solution for developers to quickly and inexpensively simulate embedded software on system-on-chip (SoC) designs.�

Through the OVP Initiative, Imperas will provide what it claims to represent $4 million worth of its own R&D effort, including:

� OVPmodels - Open source model libraries of processors, components, peripherals, and templates which others are free to use, edit/update, and copy
� OVP APIs - APIs for developing models and verification infrastructure provided with no attached licensing costs
� OVPsim � A free reference simulator delivered as an executable solution (with limits on the source code availability and licensing terms)

Imperas has solicited the participation of the industry and has already gathered an impressive group of market leaders to join the initiative including IP suppliers such as MIPS, Tensilica, Denali, and notable ESL/EDA players like EVE, Forte, Carbon Design Systems, Calypto, CriticalBlue, and others. The company is still working out the details, but currently plans to manage the initiative and host the OVP community forum itself going forward.

Imperas believes that by opening up its virtual platform technology and simulation offering to the market at large, it may be possible to drive industry-standard practices around virtual platform development and help guide the market towards improved methods of software development/system simulation on complex hardware architectures. The company anticipates that by moving the market forward in this area, it can then build its business around software verification technologies, multi-core development, and other solutions complimentary to system simulation and virtual platforms. Expect more announcements from Imperas around their products at next month�s Multicore Expo.

VDC�s View
Imperas has certainly been coy about its overall product direction prior to this point, providing only small clues about its products and where it might play in terms of the overall ESL and multi-core software development space. This announcement provides a clearer sense of how the company will approach the market going forward.

There is no question that if the industry is able to agree on a set of common set of standards for building virtual platforms (what VDC has typically referred to as the virtual system prototyping/simulation market), market participants would be in a better position to collaborate with one other, leverage existing designs, and raise the overall level of productivity in creating virtual prototypes (something that is clearly needed for virtual platform methodologies to be successful in the long run). This is something that established virtual platform vendors such as Virtutech, VaST, Synopsys, CoWare, and ARM have been driving towards for some time now (though their vision of how this is to evolve is certainly different from Imperas�s particular approach in this case).

An open source model is an interesting concept here, and the early list of participants is encouraging, especially at the semiconductor IP level. Open source software has certainly changed the landscape in numerous software markets to date, and in VDC�s opinion a move toward this type of a model has the potential to alter the dynamics of the current market. The extent to which Imperas creates an environment that fits the real needs of the broader community and shares in the development and ownership of the technology is likely a key factor to its long term appeal and success. A critical next step will be to bring more parties to the table, including big EDA tools vendors, other semi IP suppliers, and the semiconductor suppliers themselves. VDC has noted a continued investment by IC suppliers in investing in product enablement through virtual platform technologies.

Imperas�s view that an established virtual platform market is the bridge to better multi-core software development and verification is likely in line with the views of many other market participants. In fact, if the company is able to propel greater industry standardization around virtual platform design and simulation, Imperas should expect increasing competition from bigger EDA companies at the software verification level.

While it is far too early to tell what impact this will have on the market, it will be certainly be interesting to gauge the reaction of other virtual platform tools providers and the rest of the market. Richard Goering also wrote an interesting piece on this announcement earlier this week.

Posted by VDC Embedded Systems Practice at 12:55 PM