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OVP Update to Forum Members August 2012

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PostPosted: Fri Aug 10, 2012 12:03 pm    Post subject: OVP Update to Forum Members August 2012 Reply with quote

New ARM Models; New MIPS models; New OVP Platform Examples for FreeRTOS; Integration with Simulink; Integration with NEC CyberWorkBench; 64-Bit Native Simulation, ARM DS-5 Support in Imperas Professional Products; University and Research Institute Usage

New OVPsim Release Available on www.OVPworld.org
A new release of OVPsim, 20120614 was made available to users as of 22 June 2012. This release contains the new ARM and MIPS processor core models discussed below, the new OVP example platforms with FreeRTOS, as well as fixing a number of bugs and enhancing the OVP APIs. Please check the release notes for more details.
Imperas OVP Fast Processor Models of ARM Cortex-R4 and R4F, and ARM1176JZ-S Are Released

The ARM Cortex-R4 and R4F cores are ARM's workhorse processor cores for deeply embedded systems. The ARM1176JZ-S was a very popular core for both mobile and other applications, and is still in the market today in a number of semiconductor devices. As is usual with OVP Fast Processor Models, example virtual platforms are available, showing various applications from simple benchmarks to booting Linux. And they have the usual OVP characteristics: - 100s of millions of instructions per second performance - Native interfaces for OVP C and SystemC/TLM-2.0 virtual platforms - Working with OVPsim, software running on these models can be debugged using GDB and Eclipse The new models can be downloaded from www.OVPworld.org/ARM. OVP Fast Processor Models of ARM Cores are available for ARMv4, v5, v6, and v7 architectures, and have support for additional instructions including MMU, MPU, TCM, Thumb, Thumb-2, Jazelle, SIMD, VFP, NEON, TrustZone, ... ARM cores available from OVP:
ARM7TDMI / 7EJ-S / 720T
ARM920T / 922T, 926EJ-S / 940T / 946E / 966E / 968E-S
ARM1136J-S / 1156T2-S / ARM1176JZ-S
Cortex-A5UP / Cortex-A8 / Cortex-A9UP / Cortex-A9-MP
Cortex-M3 / Cortex-M4
Cortex-R4 / Cortex-R4F

Imperas OVP Fast Processor Models of MIPS Aptiv Generation Processor Cores and MIPS64 Architecture Are Released

OVP Fast Processor Models of MIPS Technologies cores have been available from the beginning of the OVP initiative. This includes single core processors, multithreaded and multicore processors. The Aptiv Generation of processor cores from MIPS, announced in May, are the latest from MIPS. The Aptiv processors include the microAptiv, interAptiv and proAptiv families of cores. We have also released models of the MIPS 5K family of cores, based on the MIPS64 architecture. These models, as with the other OVP models of the MIPS processors, were verified by MIPS as part of their MIPS-Verified program. The new Aptiv and MIPS64 models, and the other OVP Fast Processor Models of the MIPS cores, can be downloaded from www.OVPworld.org/MIPS. MIPS cores available from OVP have support for MIPS32, microMIPS and MIPS64 instruction sets, including the MIPS16, MIPS16e, DSP, floating point, and multithreading instructions:
Single core MIPS32 M4K, 4KEm / Ec / Ep, 24KEc / KEf / Kc / Kf, 74Kc / Kf
Dual core MIPS32 34Kc / Kf
Quad core MIPS32 1004Kc / Kf, 1074Kc / Kf
microMIPS MIPS32 M14K / Kc
Aptiv Generation cores: microAptiv, interAptiv and proAptiv
Single core MIPS64 5Kc, 5Kf, 5KEc, 5KEf

Integration with Simulink
Simulink, from Mathworks, is a very popular system simulation tool used in a variety of industries. Recently two OVPsim users have taken different approaches to integrating OVPsim with Simulink. Their discussion can be found on the OVP Forum. The integration done by Frank Pippen of OFFIS (Germany) was previously announced by Imperas; you can find the announcement on the OVP News & Events page. The integration done by Francisco Mendoza of FZI (Germany) was presented at the 1st IFAC Conference on Embedded Systems, Computational Intelligence, and Telematics in Control, held in Germany in April 2012. A copy of the paper can be requested from info@OVPworld.org.

NEC's CyberWorkBench and Imperas OVP Fast Processor Models Integrated to Expand Hardware-Software Co-Verification Capabilities
OVPsim and the OVP Fast Processor Models have been integrated with NEC's CyberWorkBench (CWB) SystemC cycle-accurate hardware models. OVP's position as the de facto source of instruction accurate processor core models provides additional value to CyberWorkBench's complete C/SystemC SoC design flow including ANSI-C/SystemC synthesis, hardware-software (HW/SW) co-verification and C-based formal verification. CyberWorkBench is a C-based electronic circuit design platform developed by NEC over the course of twenty years. CyberWorkBench is developed around the "All-in-C" paradigm that allows high level synthesis and verification of any ANSI-C or SystemC program generating high quality circuits. CyberWorkBench also includes software co-simulation environments and source code debuggers. For more information, see the announcement on the OVP News & Events page.

Imperas Professional Products – 64-Bit Native Simulation, ARM DS-5 Support Available
In addition to the products available via OVP, the Imperas professional products have also been enhanced. For example, we've added a complete native 64-bit version of the simulator to the product line. Also, if you are using the ARM DS-5 tool chain, semi-hosting for DS-5 (Angel Traps) is now supported in the Imperas professional products. This support is not available in OVPsim. Contact Imperas for more details about the latest commercial products.

University and Research Institute Usage of OVP
There have been registrations from over 100 different universities on the OVP website. Some of the more recent universities that have adopted OVP include
Iowa State University, United States
Nagoya University, Embedded and Real-Time Systems Laboratory, Japan
National Tsing Hua University, Taiwan
OFFIS, Germany
Swedish Institute of Computer Science, Sweden
We are going to provide some space on the OVP website for publishing links to your work which used OVP. So when you publish or present, please send us the details of the work, as well as the link. Thanks. In addition to the FZI publication referenced in the Simulink integration section above, here's a recent publication from the University of Texas: Andreas Gerstlauer, Suhas Chakravarty, Manan Kathuria, and Parisa Razaghi, "Abstract System-Level Models for Early Performance and Power Exploration," URL: http://users.ece.utexas.edu/~gerstl/publications/aspdac12.hcm.pdf

OVPsim Current Release
The current release is 20120614, as discussed above.

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