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PriyamvadAcharya
Joined: 25 Sep 2019 Posts: 35
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Posted: Wed Oct 09, 2019 1:03 am Post subject: How to integrate SystemC model in OVP environment |
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Hello OVP Forum members,
I am working on a project where we have a peripheral model written in systemc .This peripheral model need to be linked in OVP environment so that with the help of OVPsim simulator we can execute a application on peripheral model.
We will be using RISC-V as processor model.
So I want to ask what is the process of achieving it.
With Regards,
Priyamvad Acharya
R&D Engineer |
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DuncGrah OVP Technologist

Joined: 27 Feb 2008 Posts: 1646 Location: United Kingdom
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Posted: Thu Oct 10, 2019 3:52 am Post subject: |
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Do you have a SystemC platform already in which you can execute your peripheral model?
If so then you will need to instance the OVP processor into this platform, if not you will need to create a SystemC platform.
The OVP models are provided with SystemC TLM2.0 interface files which allow them to be instanced into a SystemC platform.
We have an example in Examples/PlatformConstruction/SystemC_TLM which generates an example TLM platform. This uses our own defintion of a bus decoder so direct TLM b_transport to another device or memory.
There is also the document Imperas/doc/ovp/OVPsim_Using_OVP_Models_in_SystemC_TLM2.0_Platforms.pdf that describes OVP processors in SystemC and this example
You may want to think about modifying this platform defintion to add an OVP peripheral, generate the TLM platform and then see if you can exchange the OVP peripheral for your own SystemC peripheral.
I would suggest you could generate an OVP peripheral template with the corrrect interface as your own and use this so that you get the correct signals connected.
Hope that helps get you started. |
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PriyamvadAcharya
Joined: 25 Sep 2019 Posts: 35
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Posted: Fri Oct 11, 2019 4:48 am Post subject: |
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How to modify platform defintion to add an OVP peripheral, generate the TLM platform. |
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PriyamvadAcharya
Joined: 25 Sep 2019 Posts: 35
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Posted: Fri Oct 11, 2019 4:54 am Post subject: |
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Hello DuncGraph,
How to create SystemC platform.
I only have peripheral model written in SystemC.
I am attaching my peripheral model file for your reference.
Code: | //agnisys, inc. ***** copyright 2016 all rights reserved. *****
//
//*** This file is auto generated by IDesignSpec (http://www.agnisys.com) . Please do not edit this file. ***
// created by :
// generated by : Agnisys01
// generated from : C:\Users\Agnisys01\Documents\block.docx
// IDesignSpec rev : idsbatch v6.16.12.0
//*** This code is generated with following settings ***
// Reg Width : 32
// Address Unit : 8
// C++ Types int : hwint
// Bus Type : PROPRIETARY
// BigEndian : true
// LittleEndian : true
// Dist. Decode and Readback : false
//---------------------------------------------------------------------------------------------------------------
#include "C:\systemc-2.3.3\src\systemc.h"
#include "block_name1_module.h"
void block_name1_ids::main()
{
//Reset Section -- REG_NAME1
reg_name1_F1_q = 0b00000000000000000000000000000000;
wait();
while(true) //clocked process
{
sc_bv<4> byte_enb = byteenable;
sc_bv <32> reg_enb;
reg_enb.range(31,24) = byte_enb[3] == 1 ? 0b11111111 : 0;
reg_enb.range(23,16) = byte_enb[2] == 1 ? 0b11111111 : 0;
reg_enb.range(15,8) = byte_enb[1] == 1 ? 0b11111111 : 0;
reg_enb.range(7,0) = byte_enb[0] == 1 ? 0b11111111 : 0;
//----------------------------------------------------------------------------------------------------
// REGISTER : REG_NAME1 ADDRESS : 0x0 WIDTH : 32
// HW ACCESS : READ-WRITE SW ACCESS : READ-WRITE
// FIELDS :
// 31:0 : F1 ( SW : Read-Write HW : Read-Write )
//-----------------------------------------------------------------------------
// DESCRIPTION : NA
//
//----------------------------------------------------------------------------
// FIELD : F1
// DESCRIPTION : NA
//-----------------------------------------------------------------
if (reg_name1_F1_in_enb) // F1 : HW Write
{
reg_name1_F1_q = reg_name1_F1_in;
} else if (reg_name1_wr_valid) // F1 : SW Write
{
reg_name1_F1_q = ( wr_data.read().range(31,0) & reg_enb.range(31,0) ) | (reg_name1_F1_q.read() & (~reg_enb.range(31,0)));
}
else {
reg_name1_F1_q = reg_name1_F1_q ;
}
wait();
}
}
void block_name1_ids::wires()
{
//----------------------------------------------------------------------------------------------------
// REGISTER : REG_NAME1 OFFSET : 0x0 WIDTH : 32
sc_bv<2> reg_name1_offset = block_name1_offset + 0x0;
reg_name1_decode = (address.read() == reg_name1_offset) ? 0b1 : 0b0;
reg_name1_wr_valid = reg_name1_decode && wr_stb;
reg_name1_enb = reg_name1_wr_valid;
// HW OUTPUT READ DATA FOR EACH FIELD
reg_name1_F1_r = reg_name1_F1_q ; // Field : F1
sc_bv<32> temp_reg_name1=0;
if (reg_name1_decode)
{
temp_reg_name1.range(31,0) = reg_name1_F1_q.read();
}
reg_name1_rd_data = temp_reg_name1;
//----------------------------------------------------------------------------------------------------
rd_data = reg_name1_rd_data.read();
request = 1;
rd_data_vld = rd_stb;
rd_wait = 1;
}
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Thanks,
Priyamvad |
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DuncGrah OVP Technologist

Joined: 27 Feb 2008 Posts: 1646 Location: United Kingdom
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Posted: Fri Oct 11, 2019 5:23 am Post subject: |
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Ok, I see this is trivial SystemC peripheral. OVP is instruction accurate and as such uses the TLM2.0 interface. For your peripheral to work in this environment you will need to create a SystemC TLM2.0 interface for your SystemC peripheral.
Do you need to use SystemC at all, I notice that your company has a tool that generates peripheral interfaces, have you thought about generating an OVP description instead?
You could generate the input to the iGen tool which is a list of registers and bit fields.
If you do wish to use your SysyemC peripheral with OVP I suggest you create an OVP SystemC platform with a peripheral with a similar interface as yours and then modify this so that the TLM2.0 b_transport transactions are converted to low level SystemC access to your peripheral.
I hope this makes sense to you? |
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PriyamvadAcharya
Joined: 25 Sep 2019 Posts: 35
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Posted: Fri Oct 11, 2019 9:07 am Post subject: |
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Is it necessary to use iGen tool ,if not how we can do it? |
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PriyamvadAcharya
Joined: 25 Sep 2019 Posts: 35
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Posted: Fri Oct 11, 2019 11:30 pm Post subject: |
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Hello DuncGraph,
What is OVP description and how we can do it.
Its my starting project in virtual platform modelling so tell me the steps of how to do it from starting to end so I can clearly understand things.
Please use example for explanation.
Thanks
Priyamvad Acharya |
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DuncGrah OVP Technologist

Joined: 27 Feb 2008 Posts: 1646 Location: United Kingdom
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Posted: Mon Oct 14, 2019 12:03 am Post subject: |
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Please start with the example and docuemnt as mentioned previously
Quote: | We have an example in Examples/PlatformConstruction/SystemC_TLM which generates an example TLM platform. This uses our own defintion of a bus decoder so direct TLM b_transport to another device or memory.
There is also the document Imperas/doc/ovp/OVPsim_Using_OVP_Models_in_SystemC_TLM2.0_Platforms.pdf that describes OVP processors in SystemC and this example |
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PriyamvadAcharya
Joined: 25 Sep 2019 Posts: 35
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Posted: Mon Oct 14, 2019 12:49 am Post subject: |
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Hello DuncGraph,
How to generate OVP description?
What exactly is OVP description. |
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DuncGrah OVP Technologist

Joined: 27 Feb 2008 Posts: 1646 Location: United Kingdom
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Posted: Mon Oct 14, 2019 1:41 am Post subject: |
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Probably not the best terminology I used.
When I said "OVP description instead" I meant generate an OVP peripheral model and use this with the OVP simulator instead of using SystemC.
See the document doc/ovp/OVP_Peripheral_Modeling_Guide.pdf and doc/ovp/iGen_Peripheral_Generator_User_Guide.pdf
This will provide you with a simulation environment in which you can use the OVP processor models and peripherals more easily. |
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PriyamvadAcharya
Joined: 25 Sep 2019 Posts: 35
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Posted: Mon Oct 14, 2019 3:33 am Post subject: |
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Okay DuncGraph
I will try generating OVP peripheral model. |
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PriyamvadAcharya
Joined: 25 Sep 2019 Posts: 35
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Posted: Mon Oct 14, 2019 5:19 am Post subject: |
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Hello DuncGraph,
Thanks for support,
I am using below command
make -C module NOVLNV=1
to build module part in /c/Imperas/Examples/Models/Peripherals/creatingDMAC/1.registers directory .
I am getting below error
error: #error "Please use -mno-cygwin flag to gcc/cygwin compiler"
How to fix this error? |
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DuncGrah OVP Technologist

Joined: 27 Feb 2008 Posts: 1646 Location: United Kingdom
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Posted: Tue Oct 15, 2019 11:57 pm Post subject: |
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You have Cygwin installed on your machine and this is a check that is in the included file Imperas/ImpPublic/include/hostapi/impTypes.h
What is the environment you are building in? We require MSYS on Windows.
Can you remove the Cygwin environment, which is not required for OVP?
Or can you ensure that you are not using the Cygwin compiler when building. |
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PriyamvadAcharya
Joined: 25 Sep 2019 Posts: 35
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Posted: Mon Oct 21, 2019 4:38 am Post subject: |
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Hello DuncGraph,
I have Msys installed on Windows.
I have also installed mingw compiler toolchain for both 32 bit and 64 bit version.
I have removed Cygwin from windows but still this error comes :-error: #error "Please use -mno-cygwin flag to gcc/cygwin compiler.
How could I ensure that Cygwin compiler is not used during building process?
I have tried from my part but still error persists.
Please help me to solve this problem. |
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DuncGrah OVP Technologist

Joined: 27 Feb 2008 Posts: 1646 Location: United Kingdom
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Posted: Mon Oct 21, 2019 5:23 am Post subject: |
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It looks like the error is generated when __CYGWIN__ is defined, see Imperas/ImpPublic/include/host/hostapi/impTypes.h, could this still be set somewhere? |
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