OVP Forums - A community of assistance, help, questions, and answers.
  FAQFAQ    SearchSearch      RegisterRegister  ProfileProfile    Log in to check your private messagesLog in to check your private messages    Log inLog in
Charcterization of c application

 
Post new topic   Reply to topic    Open Virtual Platforms Forum Index -> Ask a Question
View previous topic :: View next topic  
Author Message
SunilRathod



Joined: 06 Jun 2019
Posts: 26

PostPosted: Sun Sep 15, 2019 7:24 pm    Post subject: Charcterization of c application Reply with quote

The characterization of a C application code is to be carried out using the ./RUN_STAGES.sh script file for the RISCV32GC variant.
Issue 1: The makefile is configured appropriately to obtain instruction accurate simulation and the results are obtained. To obtain the cycle approximate simulation for the same code using select option 2, the following error is obtained, “Fatal (CPUEST_PNS) exTT: processor type ‘riscv’ with variant ‘RV32GC’ is not supported”.
Issue 2: The following error occurs for instruction accurate simulation of C application with floating point instructions using RV32GC variant “Warning (RISCV_ADF) CPU ‘iss/cpu0’ a5: Illegal instruction – extension D (double-precision floating point) absent or inactive”. How can I enable the single precision and double precision floating point for the RV32GC variant.
Issue 3: In order to obatin the memory cycles for a c application, suggest me the appropriate commands to be used in iss.exe command line within the terminal
Kindly guide us in resolving the issues.
Back to top
View user's profile Send private message
DuncGrah
OVP Technologist
OVP Technologist


Joined: 27 Feb 2008
Posts: 1656
Location: United Kingdom

PostPosted: Mon Sep 30, 2019 7:46 am    Post subject: Reply with quote

Issue 1
This Example provides a simple timing library to show how this can be implemented/extended for RISC-V custom instructions.
The library contains only the base instructions and so has been configured to check that only a base processor variant is used.
Please have a look in the function ceGetProcInfo around line 309 in Imperas\Examples\Models\Processor\FeatureUsage\RISCV_CustomInstructionFlow\timingToolLib\timingTool.c
Code:
    if(strcmp(type, "riscv")) {
        // not a RISCV model variant
    } else if(!strcmp(variant, "RV32IM")) {
        result = &infoRISCV;
    }

which can be extended to allow other variants to be used
Code:
    if(strcmp(type, "riscv")) {
        // not a RISCV model variant
    } else if(!strcmp(variant, "RV32IM") || !strcmp(variant, "RV32GC")) {
        result = &infoRISCV;
    }


BUT when doing this please be aware that not all instruction timings may have been added for the additional instructions of this variant!

Issue 2
If you are selecting variant RV32GC this should include MAFD so the D extension should be present. Please can you provide more detail on what you are running, are you sure the configuration is correct?

Issue 3
The iss.exe is a virtual platform that is intended to allow the execution of C algorithms. Additional tools can be added to the simulation using the Imperas professional product. These could be custom tools you can create using standard APIs to allow you to analyses your application, this can include analyzing memory usage, I think this is what you should consider.
Back to top
View user's profile Send private message Visit poster's website
SunilRathod



Joined: 06 Jun 2019
Posts: 26

PostPosted: Wed Oct 16, 2019 11:36 pm    Post subject: cycle accurate simualtion Reply with quote

The error remained same even after changing the timingtool.c file in line 309
i.e.,
} else if(!strcmp(variant, "RV32IM") || !strcmp(variant, "RV32GC")) {
result = &infoRISCV;

With error message as
Fatal (CPUEST_PNS) exTT: processor type 'riscv' with variant 'RV32GC' is not supported. Contact Imperas info@imperas.com
Info Exiting


Please do the needful

Thanks in advance
Back to top
View user's profile Send private message
DuncGrah
OVP Technologist
OVP Technologist


Joined: 27 Feb 2008
Posts: 1656
Location: United Kingdom

PostPosted: Thu Oct 17, 2019 7:17 am    Post subject: Reply with quote

Can you print the variant variable and see what it is set to?

Do you set the variant to RV32GC or are you using the add_Extensions parameter to add new extensions? The value of the variant variable will be set differently and you may need to allow both.
Back to top
View user's profile Send private message Visit poster's website
SunilRathod



Joined: 06 Jun 2019
Posts: 26

PostPosted: Sun Oct 20, 2019 7:52 pm    Post subject: cycle accurate simualtion Reply with quote

The variant variable when executing the instruction accurate simulation is RV32GC, which is printed in the simulation statistics
i.e., Variant=RV32GC
The variant is set to RV32GC and not using add_extensions parameter. But the error remained same.
Kindly suggest the procedure for obtaining the cycle count
Back to top
View user's profile Send private message
SunilRathod



Joined: 06 Jun 2019
Posts: 26

PostPosted: Sun Oct 20, 2019 8:37 pm    Post subject: cycle accurate simualtion Reply with quote

Thanks a lot for the Imperas team for your support. The cycle accurate simulation is obtained for RV32GC and RV32IMAC variants.

The issue is with buildutils in the ImperasLib directory and is resolved know.

Thanking You :D
Back to top
View user's profile Send private message
DuncGrah
OVP Technologist
OVP Technologist


Joined: 27 Feb 2008
Posts: 1656
Location: United Kingdom

PostPosted: Sun Oct 20, 2019 11:09 pm    Post subject: Reply with quote

Please can you describe the problem and the solution so that other users are aware. Thanks.
Back to top
View user's profile Send private message Visit poster's website
SunilRathod



Joined: 06 Jun 2019
Posts: 26

PostPosted: Mon Oct 21, 2019 8:46 pm    Post subject: cycle accurate simualtion Reply with quote

The timingtool.c is extended as per your guidelines in the above posts. But when I am trying to build it, the buildutild in the ImperasLib is getting deleted automatically, but the reason is unknown. And replaced the file back in the same directory and tried to execute and finally obtained the results.

If possible can you suggest the reason, why this folder is been deleted repeatedly

Thanking you
Back to top
View user's profile Send private message
DuncGrah
OVP Technologist
OVP Technologist


Joined: 27 Feb 2008
Posts: 1656
Location: United Kingdom

PostPosted: Mon Oct 21, 2019 11:10 pm    Post subject: Reply with quote

Sorry i do not recognise that name builtutild as a directory in ImperasLib

Please can you explain in more detail what you are doing

If you add VERBOSE=1 to any comamnd line invoking make you will obtain more information what is going on.
Back to top
View user's profile Send private message Visit poster's website
SunilRathod



Joined: 06 Jun 2019
Posts: 26

PostPosted: Wed Oct 23, 2019 12:41 am    Post subject: cycle accurate simualtion Reply with quote

Hello sir, sorry it is actually buildutils in ImperasLib

When I extended the timingtool.c file with RV32IMAC variant, the issue is obtained as RV32IMAC variant is not supported. Then, I have tried to clean it using make clean command and errors occured as follows:

/c/Imperas/Examples/Models/Processor/FeatureUsage/RISCV_CustomInstructionFlow
$ make clean
make -C instructionExtensionLib NOVLNV=1 clean
make[1]: Entering directory `/c/Imperas/Examples/Models/Processor/FeatureUsage/RISCV_CustomInstructionFlow/instructionExtensionLib'
make[1]: Leaving directory `/c/Imperas/Examples/Models/Processor/FeatureUsage/RISCV_CustomInstructionFlow/instructionExtensionLib'
make -C instructionExtensionCFunctionCallLib NOVLNV=1 clean
make[1]: Entering directory `/c/Imperas/Examples/Models/Processor/FeatureUsage/RISCV_CustomInstructionFlow/instructionExtensionCFunctionCallLib'
make[1]: Leaving directory `/c/Imperas/Examples/Models/Processor/FeatureUsage/RISCV_CustomInstructionFlow/instructionExtensionCFunctionCallLib'
make -C application clean
make[1]: Entering directory `/c/Imperas/Examples/Models/Processor/FeatureUsage/RISCV_CustomInstructionFlow/application'
rm -f test_c.RISCV32.elf test_asm.RISCV32.elf test_c.RISCV32.od test_asm.RISCV32.od test_main.RISCV32.o test_lib_c.RISCV32.o test_main.RISCV32.o test_lib_asm.RISCV32.o exception.RISCV32.elf
make[1]: rm: Command not found
make[1]: [clean] Error 127 (ignored)
make[1]: Leaving directory `/c/Imperas/Examples/Models/Processor/FeatureUsage/RISCV_CustomInstructionFlow/application'
make -C C:/Imperas/ImperasLib/source/riscv.ovpworld.org/processor/riscv/1.0/model clean VLNVROOT=C:\Imperas\ImperasLib\buildutils OBJROOT=C:\Imperas\ImperasLib\buildutils/riscv.ovpworld.org/processor/riscv/1.0/model/obj
make[1]: Entering directory `/c/Imperas/ImperasLib/source/riscv.ovpworld.org/processor/riscv/1.0/model'
make[1]: Leaving directory `/c/Imperas/ImperasLib/source/riscv.ovpworld.org/processor/riscv/1.0/model'
rm -rf C:\Imperas\ImperasLib\buildutils
make -C timingToolLib NOVLNV=1 clean
make[1]: Entering directory `/c/Imperas/Examples/Models/Processor/FeatureUsage/RISCV_CustomInstructionFlow/timingToolLib'
Makefile:7: C:/Imperas/ImperasLib/buildutils/Makefile.host: No such file or directory
make[1]: *** No rule to make target `C:/Imperas/ImperasLib/buildutils/Makefile.host'. Stop.
make[1]: Leaving directory `/c/Imperas/Examples/Models/Processor/FeatureUsage/RISCV_CustomInstructionFlow/timingToolLib'
make: *** [clean] Error 2

And when trying to build the libraries, the errors are obatined indicating the absence of buildutils.

/c/Imperas/Examples/Models/Processor/FeatureUsage/RISCV_CustomInstructionFlow
$ ./RUN_STAGES.sh
Libraries not built, building now ...
make -C application
make[1]: Entering directory `/c/Imperas/Examples/Models/Processor/FeatureUsage/RISCV_CustomInstructionFlow/application'
make[1]: Nothing to be done for `all'.
make[1]: Leaving directory `/c/Imperas/Examples/Models/Processor/FeatureUsage/RISCV_CustomInstructionFlow/application'
make -C instructionExtensionCFunctionCallLib NOVLNV=1
make[1]: Entering directory `/c/Imperas/Examples/Models/Processor/FeatureUsage/RISCV_CustomInstructionFlow/instructionExtensionCFunctionCallLib'
Makefile:6: C:/Imperas/ImperasLib/buildutils/Makefile.host: No such file or directory
make[1]: *** No rule to make target `C:/Imperas/ImperasLib/buildutils/Makefile.host'. Stop.
make[1]: Leaving directory `/c/Imperas/Examples/Models/Processor/FeatureUsage/RISCV_CustomInstructionFlow/instructionExtensionCFunctionCallLib'
make: *** [instructionExtensionCFunctionCallLib/model.dll] Error 2


I couldn't know the reason why this folder is getting deleted?

But when the folder is replaced back the issue being resolved.


Issue 2: Can you please suggest me the command line for adding double floating point extensions using add_extensions/ or misa_extensions
Back to top
View user's profile Send private message
DuncGrah
OVP Technologist
OVP Technologist


Joined: 27 Feb 2008
Posts: 1656
Location: United Kingdom

PostPosted: Wed Oct 23, 2019 1:03 am    Post subject: Reply with quote

It is very worrying that something is deleting directories from your installation.

I would suggest that you
1) ensure you are working from a copy of the RISCV_CustomInstructionFlow and are not working within the release installation.
2) un-install the current release and re-install to ensure no other corruptions
3) verify that the changes that you have made in the example could not be causing this issue.

Check that the environment is setup correctly.

Please check the documenation for the RISC-V model Imperas\ImperasLib\source\riscv.ovpworld.org\processor\riscv\1.0\doc

You will see that the parameter add_Extensions that can be used to enable additional extensions, for exampe add_Extensions=D will add the double precision floating point. remeber that you must enable the floating point unit before you can use it, either in the applciation code writing tot he status register or using the parameter mstatus_FS
Back to top
View user's profile Send private message Visit poster's website
SunilRathod



Joined: 06 Jun 2019
Posts: 26

PostPosted: Tue Nov 05, 2019 3:35 am    Post subject: CPU cycle count for RV32GC variant and base timing library Reply with quote

Kindly clarify the below mentioned issues:

1. For RV32GC variant, I want to find how many CPU cycles are required for execution of each instruction

I have searched a lot to find out that how many clock is needed for operation of each instruction in ISA RV32GC variant, but I couldn’t find any thing.

2. The base timing information is available for RV32IM variant in the timingtool.c file, may I know the procedure to add the base timing information for RV32GC variant. Kindly suggest

Thanks in advance
Back to top
View user's profile Send private message
DuncGrah
OVP Technologist
OVP Technologist


Joined: 27 Feb 2008
Posts: 1656
Location: United Kingdom

PostPosted: Tue Nov 05, 2019 3:51 am    Post subject: Reply with quote

There are two approaches
1) the easiest is probably to take a copy of the timingToolLib directory and then update the files to require the RV32GC variant to be used
2) alternativley, you could extend the current timingTool C file to allow configuration based upon the variant to select the correct timing information.

In either case you will need to update the C file to include new instruction timings, inter-instruction delays etc for the RV32GC variant.

I am not sure where you can currently find these timings, they would typically be provided as part of the detailed specification provided by an IP vendor. Therefore, you may want to look at an IP Vendor that is providing a core including the RV32GC to get this information.
Back to top
View user's profile Send private message Visit poster's website
MadanMohan



Joined: 31 May 2019
Posts: 7

PostPosted: Mon Nov 11, 2019 7:24 am    Post subject: RISCV Cores timing information Reply with quote

As mentioned in the post, based timing information depends on the RISCV CORES of particular IP vendors.

Based on which RISCV core, is this Imperas timing library designed
Back to top
View user's profile Send private message
DuncGrah
OVP Technologist
OVP Technologist


Joined: 27 Feb 2008
Posts: 1656
Location: United Kingdom

PostPosted: Mon Nov 11, 2019 8:56 am    Post subject: Reply with quote

The example timing library in the RISC-V example is based upon general RISC-V cycle information it is not based on particular vendor IP silicon.
Back to top
View user's profile Send private message Visit poster's website
Display posts from previous:   
Post new topic   Reply to topic    Open Virtual Platforms Forum Index -> Ask a Question All times are GMT - 8 Hours
Page 1 of 1

 
Jump to:  
You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum


Information regarding OVP © 2008-2022 Imperas Software