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Reg: Tool chain support

 
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KishoreKumar



Joined: 26 May 2015
Posts: 3

PostPosted: Tue May 26, 2015 2:44 am    Post subject: Reg: Tool chain support Reply with quote

Hello,

Can we simulate ARM processor model in Xilinx ISE 14.7 tool chains ?

Regards,
Kishore Kumar K
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DuncGrah
OVP Technologist
OVP Technologist


Joined: 27 Feb 2008
Posts: 1646
Location: United Kingdom

PostPosted: Thu May 28, 2015 12:05 am    Post subject: Reply with quote

If the Xilinx crosscompiler can generate binary instructions for the ARM architecture then the OVP ARM Fast Processor Model will execute it as an instruction accurate representation of the real hardware core.

What you will need to do, as a minimum, is generate a platform that contains the processor core configured for the targeted variant and with memory at the correct memory locations.

What you may not have support for is semihosting. This is where instead of the low level routines such as open, read, write, used to implement say printf being supported by device drivers they are replaced by code that uses the native host features. So for example printf can go to the host stdout.

There must be a semihost library that represents the method used in the cross compiler toolchain supplied C libraries. I would suggest that you initially use armAngel or armNewlib depending if ARM angel traps or Newlib C functions are used in the C library.
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