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OVP Update to Forum Members February 2014

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PostPosted: Wed Feb 12, 2014 1:33 pm    Post subject: OVP Update to Forum Members February 2014 Reply with quote

Imperas Supports Imaginations MIPS Cores With Fastest Ever Processor Model Simulation

Imperas has added support for OVP models of Imagination Technologies MIPS processors to QuantumLeap ( http://www.imperas.com/quantumleap-virtual-platform-simulation-acceleration ), a parallel simulation performance accelerator. QuantumLeap leverages Imperas new synchronization algorithm to provide the fastest virtual platform software execution speed available today on standard, multi-core Personal Computer (PC) host machines. The Imperas technology - simulation plus processor core models - provides the MIPS ecosystem with the fastest software simulation solution in the industry. Performance of over 16 billion instructions per second has been achieved with QuantumLeap.

"We are delighted to be working with Imperas to deliver the fastest Instruction Accurate (IA) simulation solution for our many MIPS partners," said Tony King-Smith, EVP of marketing for Imagination Technologies. “We have been impressed how Imperas simulation technology significantly outperforms other commonly-used solutions. Faster simulation results in more tests being run, and therefore higher quality software being developed - and that is good news for our extensive MIPS ecosystem community. Since acquiring MIPS, Imagination has committed to working more closely with innovative partners like Imperas to deliver superior CPU modelling solutions. As a result, we are confident our MIPS licensees and many software ecosystem partners will have access to the best tools in the industry, enabling them to create the best possible software and products.”

Read the complete announcement on the OVP website news page.

Imperas at Embedded World: Presenting a paper; demos in partner booths

Embedded World is February 25-27 in Nuremberg, Germany. Imperas is presenting a paper titled "Customized, Intelligent Memory Access Monitoring for Reliable Asymmetric MultiProcessor System Development" in Session 23, Thursday at 14:00. We will be available for demos of the Imperas simulation and software development, debug and test tools in the Altera booth Tuesday and Wednesday from 10:00-11:00 and 14:00-15:00, and Thursday from 10:00-11:00. We will also be in the Imagination Technologies booth for demos of the Imperas tools for MIPS cores.

Here is a brief summary of the paper:

The use of Asymmetric MultiProcessor (AMP) architectures is now widespread. Two common implementations are Linux running on one core of a dual-core ARM Cortex-A9, with an RTOS running on the other, and SMP Linux running on the dual-core ARM Cortex-A9 and an RTOS or bare metal application running on another processor core, such as an Altera NIOS II. The reliability of such a system is highly dependent on the correct functioning of inter-core interaction with shared resources, which is often hard to verify.

This paper details the methodology used to bring up such an AMP system on a virtual platform. The first step is the construction of the instruction accurate virtual platform for the two AMP systems. The Open Virtual Platforms APIs for model and platform development are used in building the virtual platforms used in this paper. These virtual platforms are variants of the Altera SoC FPGA Cyclone V product. The second step in the process involves the use of CPU- and OS-aware analysis tools to help with initial system bring up. Rather than providing only instruction trace data, these tools enable the analysis of the system at the appropriate level of abstraction for the software engineer: C source code for firmware and drivers and the OS task/event level for operating systems. In addition, the tools are non-intrusive, requiring no instrumentation or modification of the application or OS, thus validating the results of the analysis.

Finally, the third step is the development of a robust test environment, including the use of non-intrusive, intelligent memory access monitors, built upon the CPU- and OS- aware simulation environment to ensure that different OS operations do not access forbidden memory segments.

A detailed case study illustrating how complex faults have been found in software running on an Altera Cyclone V AMP system, by using this methodology, will be shown.

Imperas at DVCon: Presenting a paper on software verification

DVCon is March 3-6 in San Jose, California. Imperas will be presenting a paper titled "Learning From Advanced Hardware Verification for Hardware Dependent Software" as part of Session 3, at 9:30am Tuesday March 4th. Here is the abstract:

We present a new perspective for embedded software verification for generalized multicore processor platforms, somewhat analogous to simulation-centric hardware verification solutions. A spatial, temporal, and abstract multi-dimensional framework for software verification, profiling, analysis, and debug is discussed that leverages a specialized simulation core. The simulator enables key services for the verification solution while providing a degree of separation from both the hardware models and software under test, to ensure accurate behavioral representation, as well as customization and performance advantages.

This paper will discuss requirements for modern embedded software development and solutions utilized to date, before discussing this simulation-based solution and the dimensional framework layered above. We will also discuss two real life scenarios where the solution is utilized to affect.

Imperas at CDNLive: Presenting a paper on the importance of simulation speed for software quality

CDNLive is March 11-12 in Santa Clara, California. Imperas is presenting a paper titled "Software Quality is Directly Proportional to Simulation Speed" as part of Track 6, at 4pm Tuesday March 11th. Here is the abstract:

"Software quality is directly proportional to simulation speed." This is obvious, even intuitive, for engineers. Faster simulations mean more tests can be run, which in turn means more bugs can be found, which results in higher quality. Reduced schedules can be a side benefit of speed.

While this is obvious, why is it so important right now? One example is server SoCs, where software/systems test suites can include hundreds of tests, each consisting of hundreds of billions of instructions. If the virtual platform performance is 100 MIPS, this test suite could take over one week to run. If the performance is five times faster, running the test suite takes 1 day; ten times faster and it runs overnight. This simulation speed is especially interesting with the new generation of ARMv8 based server SoCs that are currently under development. It is also interesting in areas such as image recognition, where hardware accelerators sit next to the CPUs on the SoC.

In this paper we discuss virtual platform simulation performance, including how to take advantage of the multiple cores on the host PC for increased simulation speed. Examples of virtual platforms with 1) ARMv8 multicore processors and 2) hardware accelerators will be shown to illustrate how simulation speed can be accelerated.

The Latest OVPsim Release is 20140127.0 (Jan 2014)
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