Access to RISC-V versification with UVM

[PiotrCzak]

Hi,

I've seen that you've announced first reference model with UVM encapsulation for RISC-V verification. However, I cannot find any more information about this on your webpage.
Could you provide me with some information and instructions.

Thank you,
Best Regards,
Piotr

[AdminiStrator]

Hi Piotr

We are making this SystemVerilog encapsulation of the OVP CPU models available as Examples/SystemVerilog in the next release of OVPsim.

This encapsulation allows step and compare hardware design verification comparing the Imperas reference models vs. RTL implementations and compares instructions, state, and asynchronous behavior.

Currently the new release is in beta test where we are ensuring it works with Cadence, Mentor, Synopsys and Metrics SystemVerilor UVM simulators.

So please keep checking for the new release.

Regards
Simon

[Moshe55]

Hi,

Do you have any update to share with us?

Thanks!

[AdminiStrator]

We have been working with the open source cores group https://www.openhwgroup.org/ since early 2019 on this and they are using Imperas OVP reference models of their cores in SystemVerilog UVM test benches with full async-lock-step-compare verification methodology - so you can visit there to see all the source etc of the encapsulation. The testbench is: https://github.com/openhwgroup/core-v-verif.

There are also many videos on the core-v-verif and Imperas reference models in SystemVerilog with UVM. Search for "riscv imperas openhw youtube"
This one is most recent: https://www.youtube.com/watch?v=SZGApzOGsFw

For OpenHW we provide a binary of the reference model.

We have not put the full encapsulation of the Imperas OVP cpu models in an OVP package for download from this OVPworld site - they are available as part of the Imperas professional packages - please contact Imperas.

thnx
Simon