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riscvOVPsimPlus: Page table entry load failed

 
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MasGia



Joined: 05 Aug 2020
Posts: 1

PostPosted: Tue Aug 03, 2021 2:46 am    Post subject: riscvOVPsimPlus: Page table entry load failed Reply with quote

Hello everyone,

I'd like to use OVPsim with the riscv-dv test suite.

I get the following error

Quote:
Info 192: 'riscvOVPsim/cpu', 0x00000000800001e6(init_user_mode+42): Machine 30200073 mret
Info mstatus 0000000a001c0000 -> 0000000a001c0080
Info 193: 'riscvOVPsim/cpu', 0x00000000000001ea: User *** FETCH EXCEPTION ***
Warning (RISCV_PTWE) CPU 'riscvOVPsim/cpu': Page table entry load failed [address=0x1ea PTEAddress=0x80017000 access=X]
Warning (RISCV_IMA) CPU 'riscvOVPsim/cpu' 0x000001ea 0000 illegal: No access permission for fetch (0x1ea)
Info mstatus 0000000a001c0080 -> 0000000a001c0000
Info mcause 0000000000000000 -> 0000000000000001
Info mtval 0000000000000000 -> 00000000000001ea


which I don't understand: according to my understanding the page table is correctly defined:
- at address 0x8001700 there should be 0x200060f1, which leads to
- 0x80018000, containing 0x200068f1, which leads to
- 0x8001a000, containing 0x200000ff, which is a valid entry

I am using this parameters
Quote:
# riscOVPsim configuration file converted from YAML
--variant RV64IMAC
--override riscvOVPsim/cpu/add_Extensions=MAC
--override riscvOVPsim/cpu/misa_MXL=2
#--override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0
--override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0
--override riscvOVPsim/cpu/unaligned=F
--override riscvOVPsim/cpu/mtvec_mask=0x0 # 0
--override riscvOVPsim/cpu/user_version=2.3
--override riscvOVPsim/cpu/priv_version=1.11
--override riscvOVPsim/cpu/mvendorid=0
--override riscvOVPsim/cpu/marchid=0
--override riscvOVPsim/cpu/mimpid=0
--override riscvOVPsim/cpu/mhartid=0
--override riscvOVPsim/cpu/cycle_undefined=F
--override riscvOVPsim/cpu/instret_undefined=F
--override riscvOVPsim/cpu/time_undefined=T
--override riscvOVPsim/cpu/reset_address=0x80000000
--override riscvOVPsim/cpu/simulateexceptions=T
--override riscvOVPsim/cpu/defaultsemihost=F
--override riscvOVPsim/cpu/wfi_is_nop=F
--override riscvOVPsim/cpu/Sv_modes=0x100
--override riscvOVPsim/cpu/ASID_bits=16
--override riscvOVPsim/cpu/PMP_grain=1
--exitonsymbol _exit


Does anyone have a suggestion how to investigate further?
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DuncGrah
OVP Technologist
OVP Technologist


Joined: 27 Feb 2008
Posts: 1630
Location: United Kingdom

PostPosted: Wed Sep 15, 2021 12:10 am    Post subject: Reply with quote

I have sent you a PM with an email address to send a test case so that we can re-produce this issue and provide you a solution.
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DuncGrah
OVP Technologist
OVP Technologist


Joined: 27 Feb 2008
Posts: 1630
Location: United Kingdom

PostPosted: Wed Sep 15, 2021 5:19 am    Post subject: Reply with quote

We have looked at the test case you provided and determined that the problem is that this processor has physical memory protection (PMP) registers, and these have not been set up by Machine mode, so Supervisor mode is unable to access any memory.
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