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About SIMULATION TIME STATISTICS

 
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YouNenghu



Joined: 24 Sep 2018
Posts: 11

PostPosted: Tue Oct 09, 2018 5:59 pm    Post subject: About SIMULATION TIME STATISTICS Reply with quote

hello,
I'm sorry to trouble you.Firstly,in the example of "hello world",when using the ISS,there will be some information about "CPU 'iss/cpu0' STATISTICS and " SIMULATION TIME STATISTICS".But when I try the example of "simpleCpuMemoryUart",there is only information about the UART.If I want to see the " SIMULATION TIME STATISTICS" this time,what should I do to make it.
Secondly,when I finish a simulation about a module,can it indicate the power consumption of the processor,the Cache hit ratio,the Bus delay and the Bus conflict in the end?Something is like "SIMULATION TIME STATISTICS" that can show the related Information one by one.
Thank you very much!
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DuncGrah
OVP Technologist
OVP Technologist


Joined: 27 Feb 2008
Posts: 1656
Location: United Kingdom

PostPosted: Wed Oct 10, 2018 2:38 am    Post subject: Reply with quote

The simulation time statistics are output when the simulator is running in verbose mode, check to see if --verbose is on the command line.

There is a basic concept to understand about instruction accurate simulations. That is the state of the processor and other devices will be (approximately) the same as the real hardware on an instruction boundary. However, this means that micro architecture effects are not modeled.

Bus protocols and bus contention are not modeled.

Cache models can be added to approximate local memory accesses, see the documentation about MMCs, the example Imperas\Examples\PlatformConstruction\transparentMMC is one showing them being added using cache models from the library, for example Imperas\ImperasLib\source\ovpworld.org\mmc\wb_1way_32byteline_256tags\1.0\model

Imperas, with the commercial tools, have some initial tools to allow the approximate timing and power to be analyzed. There is work using them at a number of universities and also on the European SafePower project.
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YouNenghu



Joined: 24 Sep 2018
Posts: 11

PostPosted: Mon Oct 22, 2018 7:46 pm    Post subject: Reply with quote

Hi,
I am sorry to trouble you.Thank you for your reply.And bus protocols and bus contention are not modeled,but how can it model the different system?For example,the cortex-a9 uses AXI bus,but POWER PC uses the PCI bus.How to distinguish them if we do not have bus model.
Addition,I do not find the information about clk.Is there the concept of a clock?
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