A cooperating many-core NIOS

[JaVe]

I am looking for the quickest and simplest way to implement my idea, a kind of many-core processor, which works as a super-processor with single threads.
I do have a C++ "architecture-only" simulator already, and now I want to turn it to an instruction-level simulator.
The processor has a control level (called supervisor) above the cores, which controls and organizes the job of the cores. I plan to use NIOS custom instructions for modeling the operation of the supervisor.
To do so, I need to implement the functionality of the custom instructions and to link the signals from the custom logic to the processor signals.
For example, at the beginning only one of the cores is working, the other ones are idle until the supervisor enables them; or clone the register file in one core to another.
Is it posssible in the way I intend?
Any other (better) idea?

[DuncGrah]

Is the 'supervisor' another individual processor?

From your initial description this all appears to be straight forward.

Do you really need custom instructions in the processors?
If you decide you do, they can be added in two ways
1) using OVP you can modify the processor model source to add new instruction decodes and behavior, or
2) with Imperas you can add new instruction decodes and behavior without modifying the model by using the binary interception technology built into the Imperas professional simulator. this has the advantage that you do not modify the pre-built and tested Nios model from OVP.

[JaVe]

[DuncGrah]

This sounds like an interesting project.
I recommend that you contact Imperas at univ@imperas.com to discuss access to the Imperas professional product via the university program. I think this is well suited to adding custom instructions into the processor models without modification to the standard models.