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Relation between simulated MIPS and Nominal MIPS ?!

 
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MarwanMostafa



Joined: 07 Sep 2011
Posts: 15

PostPosted: Tue Nov 08, 2011 1:38 am    Post subject: Relation between simulated MIPS and Nominal MIPS ?! Reply with quote

Hi,
If the nominal MIPS defines the number of instructions that should be executed by a processor in a time slice, which has a default value of 100,000 instructions/time slice or 100 mips, then why does the simulated mips always exceed this value ?!

I also read in the user guide that the simulated mips exceeds nominal mips if the simulation ran faster than real time ! Would you please provide me with more insight about this ?!

Another question, I still do not get what is meant by simulated time! I am not familiar with the notion used in Verilog or Java ! Does it mean the time it takes the real hardware to execute the simulated application ?!

Thank you !
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DuncGrah
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Joined: 27 Feb 2008
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PostPosted: Tue Nov 08, 2011 4:13 am    Post subject: Reply with quote

Quote:
If the nominal MIPS defines the number of instructions that should be executed by a processor in a time slice, which has a default value of 100,000 instructions/time slice or 100 mips, then why does the simulated mips always exceed this value ?!

Yes, nominal MIPS defines the instructions for a simulated timeslice i.e. it is internal to the simulator and only really has relevance when more than a single processor is used int he target.
The simulated MIPS is the number of simulated instructions executed in real time on the host machine. So this is dependent upon the host machine and it's loading at the time of the simulation etc.

Quote:
I also read in the user guide that the simulated mips exceeds nominal mips if the simulation ran faster than real time ! Would you please provide me with more insight about this ?!

The simulator, by default, will run as fast as it can. So how many instructions it can simulate and the nominal simulation time this represent may run faster than real time. This is especially true if a 'wait' or 'sleep' or similar instruction is executed at which point the simulator can optimize the simulation to jump forward in time until the next event!

Quote:
Another question, I still do not get what is meant by simulated time! I am not familiar with the notion used in Verilog or Java ! Does it mean the time it takes the real hardware to execute the simulated application ?!

There is no Verilog or Java in OVP, why do you mention these?
Simulated time has no relevance with real hardware. This is the time within the simulation that is elapsing based upon a nominal time for each instruction.
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MarwanMostafa



Joined: 07 Sep 2011
Posts: 15

PostPosted: Tue Nov 08, 2011 5:46 am    Post subject: Reply with quote

I only mentioned Verilog and Java coz the user guide is defining the simulated time to have the same notion of time in Verilog and Java ! :)

Would you explain more what the nominal time of each instruction is ?! Do all instructions have the same nominal time or it depends on the instruction being executed?! and what is the relevance of simulated time in general ?!

Thank you...
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DuncGrah
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PostPosted: Tue Nov 08, 2011 6:16 am    Post subject: Reply with quote

If the processor is running at 100 MIPS then each instruction is assumed to have a 10nS execution time.

Simulation time is the time within the simulation. So this allows you to have a timer, clock etc.
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MarwanMostafa



Joined: 07 Sep 2011
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PostPosted: Tue Nov 08, 2011 7:45 am    Post subject: Reply with quote

Thank you
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