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  Topic: Instruction valid. But says Unimplemented CSR in OVPsimplus
RaviB

Replies: 1
Views: 172

PostForum: Ask a Question   Posted: Sun Oct 16, 2022 12:50 am   Subject: Instruction valid. But says Unimplemented CSR in OVPsimplus
Hi,
There is an instruction 7ce022f3 csrr t0,0x7ce
OVPsimplus while executing it, says: Unimplemented CSR.

Tried using "--override riscvOVPsim/cpu/Zicsr=T". But, still the same.
May ...
  Topic: mhpmcounter3 register is not holding correct value for CSRRW
RaviB

Replies: 1
Views: 323

PostForum: Ask a Question   Posted: Wed Sep 14, 2022 1:16 am   Subject: mhpmcounter3 register is not holding correct value for CSRRW
Hi,

A test has generated "csrrw a0,mhpmcounter3,gp". Assuming default value as 0 for mhpmcounter3, a0 is holding as expected.
mhpmcounter3 is WARL register and is expected to hold value ...
  Topic: Request help on understanding "ecall" instruction
RaviB

Replies: 1
Views: 310

PostForum: Ask a Question   Posted: Tue Sep 13, 2022 12:13 am   Subject: Request help on understanding "ecall" instruction
Hi Manny,

May I know what should happen in ISS when it executes ecall instruction?
Should it invoke mtvec_handler? Any exception or interrupt should be raised?

As of now it terminates with fol ...
  Topic: queries on register values for branch, multi thread, CSRRW
RaviB

Replies: 6
Views: 638

PostForum: Ask a Question   Posted: Thu Aug 18, 2022 7:22 am   Subject: queries on register values for branch, multi thread, CSRRW
Hi Manny,

Yes, I have it in my run command. But we have disabled exception handler for now. Just wanted to understand the behavior if write to Read only register will try to raise an exception or i ...
  Topic: queries on register values for branch, multi thread, CSRRW
RaviB

Replies: 6
Views: 638

PostForum: Ask a Question   Posted: Tue Aug 16, 2022 9:42 pm   Subject: queries on register values for branch, multi thread, CSRRW
Hi Manny,

Hope you are good. Thanks for your response.

1. Consider "beq s0,sp,167074994fa0". I'm using trace options "--trace --tracewrite --tracechange --tracemode --tracemem A - ...
  Topic: queries on register values for branch, multi thread, CSRRW
RaviB

Replies: 6
Views: 638

PostForum: Ask a Question   Posted: Tue Aug 16, 2022 6:25 am   Subject: queries on register values for branch, multi thread, CSRRW
Hi,

Request help on following aspects.

1.Can I can dump register values for branch related instructions?
I get to see for beq, blt, etc. I'm unable to generate registers values at that point as ...
  Topic: Unable to reconfigure misa correctly
RaviB

Replies: 2
Views: 423

PostForum: Ask a Question   Posted: Mon Aug 15, 2022 11:15 pm   Subject: Unable to reconfigure misa correctly
Hi DuncGrah,
I got the mistake I was doing. As I'm specifying mask, it is overwritten.
--override riscvOVPsim/cpu/misa_Extensions_mask=0x112f --override riscvOVPsim/cpu/add_Extensions_mask=B

Requ ...
  Topic: Unable to reconfigure misa correctly
RaviB

Replies: 2
Views: 423

PostForum: Ask a Question   Posted: Mon Aug 15, 2022 10:33 am   Subject: Unable to reconfigure misa correctly

Can you provide the test you are running so that I can run here?
What verion of the product are you running?
Thanks


Hi DuncGrah,

I'm trying to run "riscv_csr_test" with seed &quo ...
  Topic: Unable to reconfigure misa correctly
RaviB

Replies: 2
Views: 423

PostForum: Ask a Question   Posted: Sat Aug 13, 2022 4:33 am   Subject: Unable to reconfigure misa correctly
Hi,

I was trying to change default value of misa. I used following command.

$OVPSIMPLUS_PATH/riscvOVPsimPlus.exe --program test.elf --variant RV64G --override riscvOVPsim/cpu/add_Extensions=B -- ...
  Topic: OVPSIMPLUS executed an illegal instruction.
RaviB

Replies: 8
Views: 1052

PostForum: Ask a Question   Posted: Fri Aug 12, 2022 5:54 am   Subject: OVPSIMPLUS executed an illegal instruction.
Hi,

Thanks for all your time in responding to my post. I wanted to ask similar one you mentioned whether it works or not. I got the answer.
My special thanks to Lee for addressing my queries.

R ...
  Topic: OVPSIMPLUS executed an illegal instruction.
RaviB

Replies: 8
Views: 1052

PostForum: Ask a Question   Posted: Fri Aug 12, 2022 1:44 am   Subject: OVPSIMPLUS executed an illegal instruction.
Hi Lee,

Thanks a lot for elaborating.
I wanted "RV64GB". As this combination wasn't available in --showvariants, I was using "RV64GCB".
Can you suggest how to disable C when u ...
  Topic: OVPSIMPLUS executed an illegal instruction.
RaviB

Replies: 8
Views: 1052

PostForum: Ask a Question   Posted: Thu Aug 11, 2022 11:19 pm   Subject: OVPSIMPLUS executed an illegal instruction.
Hi Lee,

Thanks for your time in addressing my question. Following is the command I'm using.
$OVPSIMPLUS_PATH/riscvOVPsimPlus.exe --program file.elf --variant RV64GCB --override riscvOVPsim/cpu/sim ...
  Topic: OVPSIMPLUS executed an illegal instruction.
RaviB

Replies: 8
Views: 1052

PostForum: Ask a Question   Posted: Mon Aug 08, 2022 10:22 pm   Subject: Re: OVPSIMPLUS executed an illegal instruction.
OVPSIMPLUS has executed an instruction "f6b8" saying it as "sd".
when converted to binary, it is "1_111_01101_0111000". There is no opcode like 0111000 as per riscv spec ...
  Topic: OVPSIMPLUS executed an illegal instruction.
RaviB

Replies: 8
Views: 1052

PostForum: Ask a Question   Posted: Mon Aug 08, 2022 9:29 pm   Subject: OVPSIMPLUS executed an illegal instruction.
OVPSIMPLUS has executed an instruction "f6b8" saying it as "sd".
when converted to binary, it is "1_111_01101_0111000". There is no opcode like 0111000 as per riscv spec ...
  Topic: Is there an option available to halt on illegal: Undecoded
RaviB

Replies: 2
Views: 698

PostForum: Ask a Question   Posted: Tue Jun 28, 2022 11:30 pm   Subject: Is there an option available to halt on illegal: Undecoded
Hi Team,

In OVPsimplus, May I know if any option is available to terminate the run when illegal: Undecoded instruction is encountered?
We can see the same get's printed for several thousands of li ...
 
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