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  Topic: Unable to dump SD instruction trace information
DuncGrah

Replies: 10
Views: 142

PostForum: Ask a Question   Posted: Fri Jun 24, 2022 3:25 am   Subject: Unable to dump SD instruction trace information
I was able to get the Google test generator installed and ran with Questa

I ran with the command line you provided via PM for generator and used the generated file out_2022-06-24/asm_test/riscv_ran ...
  Topic: Unable to dump SD instruction trace information
DuncGrah

Replies: 10
Views: 142

PostForum: Ask a Question   Posted: Fri Jun 24, 2022 12:00 am   Subject: Unable to dump SD instruction trace information
I have sent a PM.
Unfortunately I am not able to run the Google test generator and it would be ideal if you could provide an ELF for me to run directly on the riscvOVPsimPlus simulator.
  Topic: Unable to dump SD instruction trace information
DuncGrah

Replies: 10
Views: 142

PostForum: Ask a Question   Posted: Wed Jun 22, 2022 8:16 am   Subject: Unable to dump SD instruction trace information
Hi Ravi,

We'd like to undertand what is happening in this case as it does not appear to be providing the information to you that you or we expect. This could just be a misunderstanding between us. ...
  Topic: elf load problem on self generated platform using igen
DuncGrah

Replies: 2
Views: 191

PostForum: Ask a Question   Posted: Wed May 25, 2022 12:03 am   Subject: elf load problem on self generated platform using igen
Hello, Glad you found the solution.
I would recomend to to -program (or equivalents) from the command line to load your programs if you want to run different programs on the virtual platform.
The re ...
  Topic: Error (RISCV/PK) SYSCALL(unhandled(*))
DuncGrah

Replies: 10
Views: 1017

PostForum: Ask a Question   Posted: Fri Apr 08, 2022 12:42 am   Subject: Error (RISCV/PK) SYSCALL(unhandled(*))
There are often issues with RISC-V toolchains and versions of the extensions they support.
For ease of use, Imperas have provided some precompiled GCC versions on their public GitHub: https://github. ...
  Topic: ETH / TCP communication
DuncGrah

Replies: 1
Views: 523

PostForum: Host Platforms   Posted: Mon Feb 28, 2022 2:42 am   Subject: ETH / TCP communication
First point to note is that the interface supports TCP/IP traffic and ping uses ICMP which is not supported so you cannot use ping to determine if the interface is alive.

The Ethernet interface mod ...
  Topic: On the time slice induced accuracy
DuncGrah

Replies: 1
Views: 581

PostForum: About Open Virtual Platforms and its EcoSystem   Posted: Thu Feb 03, 2022 5:39 am   Subject: On the time slice induced accuracy
for (1) I think you are correct. The time slice must be smaller than the minimum delay required. I think this requires a minor documentation change.

for (2) I cannot think of an obvious reason that ...
  Topic: how can monitoring at run-time the instructions executed
DuncGrah

Replies: 5
Views: 1386

PostForum: Ask a Question   Posted: Thu Nov 18, 2021 1:03 am   Subject: how can monitoring at run-time the instructions executed
There are OP API functions that allow you to monitor accesses.
You will get the data of the transaction provided in the callback, so the instruction binary on an instruction fetch. Please review the ...
  Topic: how can monitoring at run-time the instructions executed
DuncGrah

Replies: 5
Views: 1386

PostForum: Ask a Question   Posted: Wed Nov 17, 2021 6:45 am   Subject: how can monitoring at run-time the instructions executed
I am afraid there is no function available in the OP or VMI APIs that allow an instruction to be decoded. The instruction decode information is all embeded in the processor models.
There are function ...
  Topic: how can monitoring at run-time the instructions executed
DuncGrah

Replies: 5
Views: 1386

PostForum: Ask a Question   Posted: Tue Nov 16, 2021 2:05 am   Subject: how can monitoring at run-time the instructions executed
You can add callbacks onto the bus or memory that can be used to detect accesses and determine the data. Please see the monitoring functions in the OP API.
  Topic: bhmWaitDelay in instruction fetch memory access
DuncGrah

Replies: 2
Views: 2267

PostForum: Ask a Question   Posted: Fri Oct 29, 2021 12:56 am   Subject: bhmWaitDelay in instruction fetch memory access
I have re-created this issue. We have decided that this is using the peripheral model delays in a way in which they were not intended. Because the instruction is re-started after the delay the simple ...
  Topic: SystemC model and OVP environment
DuncGrah

Replies: 4
Views: 3286

PostForum: Getting started   Posted: Thu Oct 28, 2021 1:45 am   Subject: SystemC model and OVP environment
Universities can register for the Imperas University Program. This can provide access to the professional products free of charge for academic and educational usage.
Please contact univ@imperas.com
  Topic: bhmWaitDelay in instruction fetch memory access
DuncGrah

Replies: 2
Views: 2267

PostForum: Ask a Question   Posted: Wed Oct 27, 2021 11:55 pm   Subject: bhmWaitDelay in instruction fetch memory access
What you are doing looks correct, we will try to figure out what you are seeing and why it is happening .. will get back to you asap :)
  Topic: Is there a true random number generator?
DuncGrah

Replies: 2
Views: 3025

PostForum: Ask a Question   Posted: Wed Oct 27, 2021 8:36 am   Subject: Is there a true random number generator?
I don't believe that there is such a thing in a processor.
  Topic: Segmentation fault with Examples/PlatformConstruction/System
DuncGrah

Replies: 1
Views: 1545

PostForum: Ask a Question   Posted: Wed Oct 27, 2021 8:35 am   Subject: Segmentation fault with Examples/PlatformConstruction/System
It is very important that "everything" is rebuilt using the same C++ compiler and flags.
The build process has been improved in the forthcoming next release but at the moment can you try se ...
 
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