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  Topic: Error(LIC_NE) error:-5357 in Ubuntu20.04
DuncGrah

Replies: 1
Views: 848

PostForum: Licensing   Posted: Fri Oct 28, 2022 1:49 am   Subject: Error(LIC_NE) error:-5357 in Ubuntu20.04
This license failure message appears to indcate that the contents of your license file (/OVPsim_license/OVPsim.lic) does not contain the expected license feature.
  Topic: OVPsimPlus doesn't work with node-locked license :?
DuncGrah

Replies: 1
Views: 362

PostForum: Licensing   Posted: Fri Oct 28, 2022 1:41 am   Subject: OVPsimPlus doesn't work with node-locked license :?
I am afraid that riscvOVPsimPlus is not available with that type of licensing.

For information of commercial tools that can provide the same capabilities as riscvOVPsimPlus you could contact info@i ...
  Topic: PMP fetch exception
DuncGrah

Replies: 4
Views: 1670

PostForum: Ask a Question   Posted: Thu Oct 20, 2022 12:23 am   Subject: PMP fetch exception
Yes, we (Imperas) posted an issue on [url=https://github.com/riscv/riscv-isa-manual/issues/884]github requesting clarification. This has never been answered.

However, we have made changes in the cu ...
  Topic: Instruction valid. But says Unimplemented CSR in OVPsimplus
DuncGrah

Replies: 1
Views: 411

PostForum: Ask a Question   Posted: Mon Oct 17, 2022 12:39 am   Subject: Instruction valid. But says Unimplemented CSR in OVPsimplus
The CSR at 0x7CE is defined as a custom CSR (region 0x7C0-0x7FF) in the RISC-V ISA specification. It will, therefore, only be present if it is implemented by the processor you are targetting. It is no ...
  Topic: mhpmcounter3 register is not holding correct value for CSRRW
DuncGrah

Replies: 1
Views: 488

PostForum: Ask a Question   Posted: Thu Sep 15, 2022 8:27 am   Subject: mhpmcounter3 register is not holding correct value for CSRRW
The values contained in these counters are very implementation specific and as such the base model implements using the defintion from the RISCV specification that states

”All counters should be ...
  Topic: Request help on understanding "ecall" instruction
DuncGrah

Replies: 1
Views: 487

PostForum: Ask a Question   Posted: Thu Sep 15, 2022 8:02 am   Subject: Request help on understanding "ecall" instruction
When you state ISS what simulator executable are you running? iss.exe? riscvOVPsim.exe?
By default, in most of these stand-alone products, semihosting is enabled. For the RISC-V processor this is the ...
  Topic: OVPSIMPLUS executed an illegal instruction.
DuncGrah

Replies: 8
Views: 1353

PostForum: Ask a Question   Posted: Fri Aug 12, 2022 3:06 am   Subject: OVPSIMPLUS executed an illegal instruction.
Hi,

You can get what you want i.e. RV64GB using the base variant RV64G and then enabling the B extension

Please try this combination
--variant RV64B --override riscvOVPsim/cpu/add_Extensions= ...
  Topic: initsp=0 did not match anything in the platform
DuncGrah

Replies: 8
Views: 1570

PostForum: Ask a Question   Posted: Thu Jul 14, 2022 3:33 am   Subject: initsp=0 did not match anything in the platform
I understand the situation, where semihosting is enabled to handle a particular set of system calls, and is very useful for host/user interaction, it can get in the way when the application (test) wan ...
  Topic: initsp=0 did not match anything in the platform
DuncGrah

Replies: 8
Views: 1570

PostForum: Ask a Question   Posted: Wed Jul 13, 2022 6:53 am   Subject: initsp=0 did not match anything in the platform
Once I ran the example I saw the same behaviour as you are seeing.

It then became obvious that this is caused because you are disabling the default semihost (PK), which provides this feature, in yo ...
  Topic: I want to know how to write my own module or peripherals?
DuncGrah

Replies: 20
Views: 12144

PostForum: Ask a Question   Posted: Wed Jul 13, 2022 12:21 am   Subject: I want to know how to write my own module or peripherals?
Further information of the Imperas professional tools can be found at https://www.imperas.com/index.php/products

For additional information and costings please contact info@imperas.com
  Topic: Error (RISCV/PK) SYSCALL(unhandled(*))
DuncGrah

Replies: 11
Views: 2916

PostForum: Ask a Question   Posted: Wed Jul 13, 2022 12:18 am   Subject: Error (RISCV/PK) SYSCALL(unhandled(*))
I noticed that in a previous reply the link took to 404 because it included the final full-stop!
The correct link that was referred to is https://github.com/google/riscv-dv
  Topic: initsp=0 did not match anything in the platform
DuncGrah

Replies: 8
Views: 1570

PostForum: Ask a Question   Posted: Wed Jul 13, 2022 12:05 am   Subject: initsp=0 did not match anything in the platform
Can you provide this example to me? I would like to run here. I would also need the details of the version, what you installed etc.
I will PM my personal email to use if you can.
  Topic: initsp=0 did not match anything in the platform
DuncGrah

Replies: 8
Views: 1570

PostForum: Ask a Question   Posted: Tue Jul 12, 2022 4:54 am   Subject: initsp=0 did not match anything in the platform
I notice that you have added "-override riscvOVPsim/cpu/pk/initsp=1" from my example execution command line, this will likely cause an error during simulation as the SP is not aligned. I was ...
  Topic: initsp=0 did not match anything in the platform
DuncGrah

Replies: 8
Views: 1570

PostForum: Ask a Question   Posted: Tue Jul 12, 2022 4:01 am   Subject: initsp=0 did not match anything in the platform
Hi,
Can you provide the actual command line that you are using. When I try to apply an override for initsp it is working as expected.

I am wondering if perhaps you got the syntax incorrect?

Whe ...
  Topic: Unable to dump SD instruction trace information
DuncGrah

Replies: 10
Views: 1803

PostForum: Ask a Question   Posted: Fri Jun 24, 2022 3:25 am   Subject: Unable to dump SD instruction trace information
I was able to get the Google test generator installed and ran with Questa

I ran with the command line you provided via PM for generator and used the generated file out_2022-06-24/asm_test/riscv_ran ...
 
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