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  Topic: how can monitoring at run-time the instructions executed
DuncGrah

Replies: 5
Views: 454

PostForum: Ask a Question   Posted: Thu Nov 18, 2021 1:03 am   Subject: how can monitoring at run-time the instructions executed
There are OP API functions that allow you to monitor accesses.
You will get the data of the transaction provided in the callback, so the instruction binary on an instruction fetch. Please review the ...
  Topic: how can monitoring at run-time the instructions executed
DuncGrah

Replies: 5
Views: 454

PostForum: Ask a Question   Posted: Wed Nov 17, 2021 6:45 am   Subject: how can monitoring at run-time the instructions executed
I am afraid there is no function available in the OP or VMI APIs that allow an instruction to be decoded. The instruction decode information is all embeded in the processor models.
There are function ...
  Topic: how can monitoring at run-time the instructions executed
DuncGrah

Replies: 5
Views: 454

PostForum: Ask a Question   Posted: Tue Nov 16, 2021 2:05 am   Subject: how can monitoring at run-time the instructions executed
You can add callbacks onto the bus or memory that can be used to detect accesses and determine the data. Please see the monitoring functions in the OP API.
  Topic: bhmWaitDelay in instruction fetch memory access
DuncGrah

Replies: 2
Views: 1679

PostForum: Ask a Question   Posted: Fri Oct 29, 2021 12:56 am   Subject: bhmWaitDelay in instruction fetch memory access
I have re-created this issue. We have decided that this is using the peripheral model delays in a way in which they were not intended. Because the instruction is re-started after the delay the simple ...
  Topic: SystemC model and OVP environment
DuncGrah

Replies: 4
Views: 2371

PostForum: Getting started   Posted: Thu Oct 28, 2021 1:45 am   Subject: SystemC model and OVP environment
Universities can register for the Imperas University Program. This can provide access to the professional products free of charge for academic and educational usage.
Please contact univ@imperas.com
  Topic: bhmWaitDelay in instruction fetch memory access
DuncGrah

Replies: 2
Views: 1679

PostForum: Ask a Question   Posted: Wed Oct 27, 2021 11:55 pm   Subject: bhmWaitDelay in instruction fetch memory access
What you are doing looks correct, we will try to figure out what you are seeing and why it is happening .. will get back to you asap :)
  Topic: Is there a true random number generator?
DuncGrah

Replies: 2
Views: 2427

PostForum: Ask a Question   Posted: Wed Oct 27, 2021 8:36 am   Subject: Is there a true random number generator?
I don't believe that there is such a thing in a processor.
  Topic: Segmentation fault with Examples/PlatformConstruction/System
DuncGrah

Replies: 1
Views: 1034

PostForum: Ask a Question   Posted: Wed Oct 27, 2021 8:35 am   Subject: Segmentation fault with Examples/PlatformConstruction/System
It is very important that "everything" is rebuilt using the same C++ compiler and flags.
The build process has been improved in the forthcoming next release but at the moment can you try se ...
  Topic: SystemC model and OVP environment
DuncGrah

Replies: 4
Views: 2371

PostForum: Getting started   Posted: Wed Oct 27, 2021 8:26 am   Subject: SystemC model and OVP environment
The OVP simulator provides information at an instruction level. This can be used to provide some estimations.

The Imperas professional products can be used to obtain information from an executingap ...
  Topic: riscvOVPsimPlus: Page table entry load failed
DuncGrah

Replies: 2
Views: 1230

PostForum: Ask a Question   Posted: Wed Sep 15, 2021 5:19 am   Subject: riscvOVPsimPlus: Page table entry load failed
We have looked at the test case you provided and determined that the problem is that this processor has physical memory protection (PMP) registers, and these have not been set up by Machine mode, so S ...
  Topic: riscvOVPsimPlus: Page table entry load failed
DuncGrah

Replies: 2
Views: 1230

PostForum: Ask a Question   Posted: Wed Sep 15, 2021 12:10 am   Subject: riscvOVPsimPlus: Page table entry load failed
I have sent you a PM with an email address to send a test case so that we can re-produce this issue and provide you a solution.
  Topic: Demo_riscv_RV64GC_Virtio_Linux: Illegal Instruction
DuncGrah

Replies: 1
Views: 1491

PostForum: Ask a Question   Posted: Wed Sep 15, 2021 12:07 am   Subject: Demo_riscv_RV64GC_Virtio_Linux: Illegal Instruction
This appears to be a host program incompatability.

What is the host machine and OS that you are running on?

This error does not appear to be quite the same but are you running a 32-bit OVP progr ...
  Topic: Flag '--extlib' not supported in this product-OVP Simulator
DuncGrah

Replies: 1
Views: 1098

PostForum: Ask a Question   Posted: Wed Sep 15, 2021 12:01 am   Subject: Flag '--extlib' not supported in this product-OVP Simulator
There are some capabilities not available in the freely available OVPsim simulator and require the simulator available in the Imperas commercial products. The use of an extension library is by far the ...
  Topic: Running Green Hills Renesas Output elf on Renesas.OVPsim
DuncGrah

Replies: 3
Views: 1219

PostForum: Ask a Question   Posted: Tue Sep 14, 2021 11:53 pm   Subject: Running Green Hills Renesas Output elf on Renesas.OVPsim
Hi, Sorry for the late replies, but it appears that you ar making progress?

The error you are seeingProcessor Exception (PC_FIX) Executing at uninitialized address 0x400000
is caused because ther ...
  Topic: I have my own Systemc Module ,how can I connect it to VP?
DuncGrah

Replies: 1
Views: 950

PostForum: Ask a Question   Posted: Wed Sep 08, 2021 12:04 am   Subject: I have my own Systemc Module ,how can I connect it to VP?
You actually need to work the other way around!

The SystemC TLM2 platforms that are generated as examples in the OVP release are essentially closed by the way they are constructed. What you need to ...
 
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